AnnhooANNHOO TECHNOLOGY
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Annhoo office and engineering workspace

Shenzhen Engineering Team

Build complex systems that are faster and more reliable.

Annhoo is hiring FPGA, GPU, C++, Go, networking, product and business roles in Shenzhen. The team works on trading, market data, risk and infrastructure products.

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Location: Shenzhen

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9 roles currently open

Hardware Acceleration · IP Core

Senior FPGA / RTL Engineer

Design, verify and deliver trading TOE/UOE, low-latency MAC/PCS, DMA and financial-trading hardware acceleration modules that can work alongside GPU compute.

What You Will Do

  • Design low-latency protocol and data-path modules
  • Define hardware-software boundaries with GPU, C++, network and product teams
  • Build repeatable simulation, replay, pressure-test and validation flows

What We Look For

  • Strong RTL experience with Verilog, SystemVerilog or VHDL
  • Understanding of AXI, PCIe, Ethernet, DDR, SerDes or other high-speed interfaces
  • Experience with Vivado, Quartus or Synopsys flows including synthesis, placement, routing, timing constraints and timing closure
  • Board bring-up, waveform debug, simulation, validation or performance diagnosis experience is a plus
Apply for this role →
GPU Computing · Acceleration

GPU High-Performance Computing Software Engineer

Develop and optimize GPU-based software for high-performance compute, data processing, backtesting acceleration and financial analytics.

What You Will Do

  • Build GPU-accelerated data processing, backtesting, risk or analytics modules
  • Optimize CPU/GPU data paths, memory access, batching strategies and performance bottlenecks
  • Create observable and repeatable performance tests and compute-utilization evaluation flows

What We Look For

  • Experience with one or more of C++, CUDA, OpenCL or Python, with an understanding of GPU parallel-computing models
  • Understanding of GPU memory management, kernel optimization, data movement, asynchronous execution, batching and throughput tuning
  • HPC, quant backtesting, risk calculation, data analytics or inference acceleration experience is a plus
  • Able to define heterogeneous compute boundaries with FPGA, C++ backend and algorithm teams
Apply for this role →

Engineering Environment

We Take Engineering Environment Seriously

GPU, FPGA, networking and performance-observation equipment support the full workflow from development and integration to stress testing and validation.

01

Modern Office

A bright Shenzhen workspace for deep engineering, collaboration and technical client conversations.

02

GPU / FPGA Lab

GPU compute, FPGA boards, network equipment, trading links and performance observability are built into the R&D setup.

03

Performance Culture

We value measurement, code quality, review habits and cross-functional ownership over surface speed.

04

Real Financial Scenarios

Projects are close to trading, risk, market data and data-processing scenarios where engineering work matters.

Hiring Process

Clear, professional and respectful of your time.

We focus on real projects, problem decomposition and engineering judgment without unnecessary steps.

  1. 01

    Resume Review

    We focus on real projects, technical depth and ownership.

  2. 02

    Technical Interview

    Discuss system design, engineering practice and debugging experience.

  3. 03

    Team Conversation

    Align on collaboration style, project rhythm and career goals.

  4. 04

    Offer Discussion

    Discuss scope, growth path and long-term fit.